[OT] AT&T version of BSF / BSR

[Steve Maughan]

Geschrieben von:/Posted by: Steve Maughan at 26 March 2004 23:07:27:

I'm currently using Visual Studio to develop Monarch. This is fine but I'd also like to experiment with GCC. However I do have these two classic pieces of assembler in my code:
__forceinline int bsf(bitboard a)
{ __asm
{
bsf eax, dword ptr[a + 4]
add eax, 32
bsf eax, dword ptr[a]
}
};
__forceinline int bsr(bitboard a)
{ __asm
{
bsr eax, dword ptr[a]
sub eax, 32
bsr eax, dword ptr[a + 4]
add eax, 32
}
}
Since they are in Intel's format and not the AT&T format that is recognized by GCC they will not compile (even when I remove the __forceinline). Does anyone know of the AT&T equivalents to these procedure? Are there any experts that could convert them?
Thanks,
Steve Maughan

[Dann Corbit]

Geschrieben von:/Posted by: Dann Corbit at 26 March 2004 23:18:43:
Als Antwort auf:/In reply to: [OT] AT&T version of BSF / BSR geschrieben von:/posted by: Steve Maughan at 26 March 2004 23:07:27:

I'm currently using Visual Studio to develop Monarch. This is fine but I'd also like to experiment with GCC. However I do have these two classic pieces of assembler in my code:
__forceinline int bsf(bitboard a)
{ __asm
{
bsf eax, dword ptr[a + 4]
add eax, 32
bsf eax, dword ptr[a]
}
};
__forceinline int bsr(bitboard a)
{ __asm
{
bsr eax, dword ptr[a]
sub eax, 32
bsr eax, dword ptr[a + 4]
add eax, 32
}
}
Since they are in Intel's format and not the AT&T format that is recognized by GCC they will not compile (even when I remove the __forceinline). Does anyone know of the AT&T equivalents to these procedure? Are there any experts that could convert them?
Thanks,
Steve Maughan

Take a look at crafty's x86.s file.
The differences in format are pretty obvious.



my ftp site {remove http:// unless you like error messages}

[Dieter Bürßner]

Geschrieben von:/Posted by: Dieter Bürßner at 26 March 2004 23:22:21:
Als Antwort auf:/In reply to: [OT] AT&T version of BSF / BSR geschrieben von:/posted by: Steve Maughan at 26 March 2004 23:07:27:

I posted such code in CCC once. http://chessprogramming.org/cccsearch/c ... _id=256788 It is not totally exactly, what you asked, but you will probably see, how to use it. If you cannot figure out the corresponding function for the high bit, I will post it (I don't have it, yet, but it is easy, after one understood gcc inline assembly. AT&T vs. Intel is not the main issue to get it right ...)
Note, that the function (as your MSVC function) depends on undocumented behavior of x86 CPUs (CPUs don't touch the result register, when input is 0 for bsf/bsr).
Regards,
Dieter

[Dieter Bürßner]

Geschrieben von:/Posted by: Dieter Bürßner at 26 March 2004 23:27:07:
Als Antwort auf:/In reply to: Re: [OT] AT&T version of BSF / BSR geschrieben von:/posted by: Dieter Bürßner at 26 March 2004 23:22:21:

Seems, current Gcc does not like multi line strings anymore. So (untested):

__inline__ int LowBit(unsigned long long a)
{
  int res&#59;
  __asm__ volatile(
    "movl $-33, %0\n"
    "bsfl %2, %0\n"
    "addl $32, %0\n"
    "bsfl %1, %0"
  : "=q&" (res)
  : "g" ((unsigned long)a), "g" ((unsigned long)(a>>32))
  : "cc" /* condition code (flags register) clobbered */)&#59;
  return res&#59;
}

Regards,
Dieter

[Dieter Bürßner]

Geschrieben von:/Posted by: Dieter Bürßner at 26 March 2004 23:55:33:
Als Antwort auf:/In reply to: [OT] AT&T version of BSF / BSR geschrieben von:/posted by: Steve Maughan at 26 March 2004 23:07:27:

__forceinline int bsf(bitboard a)
{ __asm
{
bsf eax, dword ptr[a + 4]
add eax, 32
bsf eax, dword ptr[a]
}
};

This code looks wrong to me. Am I missing anything? To me it looks, as if would not work with (for example) bsf(0). eay seems not initialized.
Regards,
Dieter

[Dann Corbit]

Geschrieben von:/Posted by: Dann Corbit at 27 March 2004 00:42:47:
Als Antwort auf:/In reply to: Re: [OT] AT&T version of BSF / BSR geschrieben von:/posted by: Dieter Bürßner at 26 March 2004 23:55:33:

__forceinline int bsf(bitboard a)
{ __asm
{
bsf eax, dword ptr[a + 4]
add eax, 32
bsf eax, dword ptr[a]
}
};

This code looks wrong to me. Am I missing anything? To me it looks, as if would not work with (for example) bsf(0). eay seems not initialized.

It assumes that the bitboard is not zero, and also relies upon undefined behavior. "It seems to work" but the documentation warns about it.
This is from Beowulf:
FORCEINLINE
int FirstPiece(BITBOARD bits)
{
__asm {
;64 - bit number to move into ECX:EBX, will never be zero !
mov ecx, dword ptr[bits + 4]
mov ebx, dword ptr[bits]
bsf eax, ecx
add eax, 32
bsf eax, ebx
}
}
and operates under some of the same assumptions. I don't compile with it anymore anyway, since the C code compiles faster. Probably the inline assembly stumbles the optimizer.
This is what crafty does (and does not make unsafe assumptions):
FORCEINLINE int FirstOne(BITBOARD a)
{
__asm {
bsr edx, dword ptr a + 4
mov eax, 31
jnz l1
bsr edx, dword ptr a
mov eax, 63
jnz l1
mov edx, -1
l1: sub eax, edx}
}
(since the bitboards are turned around for crafty, this may be more relevant):
FORCEINLINE int LastOne(BITBOARD a)
{
__asm {
bsf edx, dword ptr a
mov eax, 63
jnz l1
bsf edx, dword ptr a + 4
mov eax, 31
jnz l1
mov edx, -33
l1: sub eax, edx}
}



my ftp site {remove http:// unless you like error messages}

[Steve Maughan]

Geschrieben von:/Posted by: Steve Maughan at 27 March 2004 23:10:05:
Als Antwort auf:/In reply to: [OT] AT&T version of BSF / BSR geschrieben von:/posted by: Steve Maughan at 26 March 2004 23:07:27:

Dann & Dieter,
Thanks for the replies! Yes I should have said that these two routines require non zero parameters. They also utilize the undocumented behavior of the BSF and BSR. I'm not too worried about this since hopefully I'll be switching to 64 bit soon and if there is a problem with 32 bit I can easily correct it. Thanks again,
Steve

I'm currently using Visual Studio to develop Monarch. This is fine but I'd also like to experiment with GCC. However I do have these two classic pieces of assembler in my code:
__forceinline int bsf(bitboard a)
{ __asm
{
bsf eax, dword ptr[a + 4]
add eax, 32
bsf eax, dword ptr[a]
}
};
__forceinline int bsr(bitboard a)
{ __asm
{
bsr eax, dword ptr[a]
sub eax, 32
bsr eax, dword ptr[a + 4]
add eax, 32
}
}
Since they are in Intel's format and not the AT&T format that is recognized by GCC they will not compile (even when I remove the __forceinline). Does anyone know of the AT&T equivalents to these procedure? Are there any experts that could convert them?
Thanks,
Steve Maughan